LMDS Synthesizer Block Diagram

MC12022 MECL prescaler data sheet

Qualcomm Q3236 PLL data sheet (8/1997) (alternate copy here is shorter but more legible)

Qualcomm Synthesizer Products (4/2000, with some rendering problems)

Phase noise 26 GHz

Pictures and Brief Description

Revised Detailed Block Diagram

SNP2627 Block Diagram

SNP 520-series Data (another MicroSource YIG synthesizer with superior PN and tuning range)

**Connection data**

Wiring Reference for 25 pin D connector MSS2527-910-04 DC200393001 PIN REF Q3236 function(s) ____________________________________________ 1 d3A3, SMODE 2 d1A13 d8M4, DBUS4, SEN\ 4 d6M2, DBUS2 5 d4M0, DBUS0 6 F LOCK 7 PWR BIT 8 +5 VDC, 700 mA 9 +15 VDC, 300 mA 10 -15 VDC, 45 mA 11 NC 12 NC 13 NC 14 d2A2, M2 WR 15 d0A0, FSELP 16 d7M3, DBUS3 17 d5M1, DBUS1 18 grnd 19 grnd 20 grnd 21 grnd 22 grnd 23 grnd 24 NC 25 NC

**Programming notes**

Calculate:N= F_{mix}/ F_{pfd}where F_{pfd}is always 5 MHz (i.e., 960 MHz / 192) and F_{mix}is the desired YTO frequency F_{yto}minus 12480 MHz (960*13). Then, calculate M and A:M= int(N/10) - 1A=N- 10(M+1) where the lower 5 bits of M are applied to these pins:M0: 5M1: 17M2: 4M3: 16M4: 3 and A is a 4-bit value applied to these pins:A0: 15A1: 2A2: 14A3: 1 Notes:

- Register value constraints:
**A**<=**M**+1,**M**= [1,31],**N**= [90,1295] - Consequently, supported values of
**N**range from 90 (**M**=8,**A**=0, F_{yto}=12930 MHz) to 329 (**M**=31,**A**=9, F_{yto}=14125 MHz) - Qualcomm Q3236 PLL chip modes are direct parallel input with legacy Q3036 behavior
- Output frequency will be 2 * F
_{yto}MHz unless you remove the doubler

**Observed residual phase noise **

Two units were driven by a common 960-MHz source, with their outputs mixed down to 400 MHz and measured with
a 3-dB correction factor. Actual residual noise is a bit better due to the nonzero IF.