This document describes the PicturePerfect ("Integrated External Video Monitor, Digitizer, Frame Buffer, and Transmitter") image capture system's video frame buffer logic, as well as the low-level actions of the image transfer software ("Image Reception and Decoding Software for Standard Parallel Interface") from the perspective of the frame buffer hardware.
Peripheral Interface for Image Data Transmission
During the development of the PicturePerfect image capture system, it was necessary to devise a means by which the host PC could download information from the image capture adapter's serially-addressable video RAM. The standard IBM parallel printer port was chosen as the system's I/O interface.
Known Prior Art:
None known to the author. Conventional AT-bus video digitizers generally employ their own address decoding and I/O- or memory-mapping logic.
Description of Invention:
Six Hitachi HM53051P video RAM ICs (U1-U6) are configured as a serially-addressable 256,000-word by 24-bit memory array. Each 4-bit IC stores half of the data necessary to represent an 8-bit red, green, or blue color value. The host begins its 24-bit pixel read cycle by asserting parallel printer port line D7, which resets the VRAM bank's address counter to 0, or top-of-frame. (A similar reset action must occur before a frame is grabbed; consequently, U10 allows either the host or the shutter circuit to reset the VRAM bank.)
Next, the host software writes a binary 000 to lines D0-D2. These three lines are decoded by U8 to yield a one-of-six chip select (#OE, or Output Enable) signal which causes one of the VRAMs to drive the four parallel Dout lines with its color nibble value while the other five remain in a high-impedance state. The first value to be written (000) causes the least significant nibble of the currently addressed pixel's red primary color value to appear at the Dout lines, which are transmitted onto four of the printer port's "handshaking" input lines by buffer U9. The host then reads the color nibble value from its printer port, and cycles through the other five D0-D2 values (001 through 101 binary), allowing it to read the remaining color nibbles for the pixel.
After all six color nibbles have been read by the host, the VRAM address counters must be incremented to point to the next pixel. When the host causes a rising edge to appear at line D6, the state machine formed by U11A and U11B allows the #CGR (Clock Gate Read) line to become active for the duration of a single cycle of the 14.318 Mhz. master clock #CLK. This increments the serial read-address counter in all six of the VRAM Ics, and the host is now able to execute another 24-bit pixel read cycle at the new location.
Refer to the attached diagram for an overview of the entire video RAM array and its support circuitry.
This circuit embodies a useful technique for transmitting 24-bit color image data through the standard IBM parallel printer port. It could be adapted for use with other imaging hardware which employs serially-addressable video memory.